Substrate Current Evaluation for Lightly and Heavily Doped MOSFETs at 45 Nm Process Using Physical Models

Substrate noise is a major integration issue in mixed signal circuits; particularly at radio frequency (RF) it becomes a key issue. In deep sub micron MOSFETs hot carrier effect induces device degradation. The impact ionization phenomenon is one of the main hot carrier effects. The paper covers the process and device level simulation of MOSFETs by TCAD and the substrate current comparison in lightly and heavily doped MOS. PMOS and NMOS devices are virtually fabricated with the help of ATHENA process simulator. The modeled devices include the hot carrier effects. The MOS devices are implemented on lightly and heavily doped substrates and substrate current is evaluated and compared with the help of ATLAS device simulator. Substrate current is better in lightly doped substrate than in heavily doped one. Drain current is also better in lightly doped than heavily doped substrates. Silvaco TCAD Tool is used for Virtual fabrication and simulation. ATHENA process simulator is used for virtual fabrication and ATLAS device simulator is used for device characterization.


Introduction
In sub-micrometer region substrate noise is of greater concern [1]. Substrate coupling in mixed signal circuits is an unavoidable and unintentional phenomenon. Any switching activity on digital part propagates to the analog by this substrate coupling, thus degrading the mixed signal circuit [2]. As the device is scaled down, hot carrier effect due to impact ionization causes reliability concern in devices and circuits [3] [4]. The resultant leakage current is studied in terms of substrate current, which constitute the substrate noise. Three broader areas are there in terms of substrate noise: noise generation, transmission and reception [5]- [7]. The substrate noise generation is a vital issue as the device scales down and is addressed in the form of hot carrier effects [8] [9].The impact ionization because of hot carrier effect can be accounted as substrate current in circuit simulators to assess the performance degradation at the circuit level due to drift in the parameters of device. Mainly in a mixed signal circuit, device level noise cumulates to degrade the overall circuit. With the ATHENA process simulator, 45nm technology devices are fabricated in this paper, further substrate current is evaluated using ATLAS device simulator. This paper reveals that lightly doped substrate is better in comparison to heavily doped substrate in terms of noise coupling as lightly doped substrate has high resistivity than heavily doped substrate. The substrate current is evaluated with respect to the gate voltage and the drain voltage, for the four devices (lightly and heavily doped PMOS and NMOS). The results validate that substrate coupling is less in lightly doped substrate than in heavily doped substrate. Section (II) describes the models used to account for the generation of the substrate current in NMOS and PMOS. Section (III) provides the description and the measurement of the device under test. In Section (IV) results are discussed. Section (V) provides Conclusion.

Modeling Substrate Current Generation
At sub-micrometer design substrate current evolves as prime leakage component. The following models from ATLAS [12] are used to model devices for substrate current generation and evaluation, matching the design geometries: impact ionization, key phenomena at RF, local electric field and temperature are accounted by it. Out of the models used, Impact ionization is the main model [16] for substrate current evaluation [17]. At higher frequency impact ionization becomes vital phenomena for device level noise.

Process and Device Simulation
Virtual fabrication of NMOS and PMOS is done with ATHENA at 45 nm technology. Device physics is involved in modeling the devices, particularly at submicron technology it plays important role. Device physics helps us to link device noise with substrate noise. Substrate noise is modeled as the sum of microscopic noise and local noise. With a decrease in channel length, impact ionization and subsequently substrate current increases [18]. The Four devices are virtually fabricated, i.e., lightly and heavily doped NMOS, lightly and heavily doped PMOS. The device width is 1um. Impact ionization model is applied to all the four modeled devices for better substrate current generation and extraction. The process steps for the devices are taken from Table 1 and Table 2  The results of process simulator are used as input for device simulator and thus device characteristics are evaluated. In this way we can study the effect of process parameters on device performance and further device structure and fabrication process can be optimized. D.C. analysis is performed for all the four devices. Threshold voltage in saturation (V t sat) and in linear region (V t lin) is determined. To determine the current driving capability of the device I on and I off are calculated. SS (sat/lin) define slope in saturation and in linear region. Calculated Drain induced barrier lowering (DIBL) accounts to the short channel effects in MOSFETs. For all the four fabricated devices the above mentioned parameters are calculated using ATLAS (SILVACO). All the calculated parameters help us to check that whether or not our fabricated device is working well. The extracted device parameters for lightly and heavily doped NMOS are given in Table 3:

Results
For all the four devices substrate current is Plotted against the gate and drain voltages. For Figure 1 I d Vs V d simulation has been done for lightly and heavily doped NMOS. Out of that substrate current (I_Sub) is extracted. During simulation we ramp our device from 0V to 1.2V for drain voltage, for different linear and saturation region gate voltages. For Figure 2 I d Vs V g simulation has been done for lightly and heavily doped NMOS. Similarly I_Sub (Substrate current) is extracted. During simulation we ramp our device from 0V to 1.2V for gate voltage, for different linear and saturation region drain voltages. From Figure 1 and Figure 2 Substrate current is more dominant in heavily doped NMOS than in lightly doped NMOS, the order of difference is almost one. These plots clearly depict that MOS with lightly doped substrate is better than heavily doped substrate in terms of substrate coupling .Substrate coupling is measured as the amount of substrate current that is further coined as substrate noise.

Conclusion
Device level noise at sub micrometer design can lead to serious circuit integration issues. Four MOS devices are virtually fabricated and their characteristics are evaluated for substrate current for lightly and heavily doped substrate. Lightly doped substrate provides better noise immunity in comparison to heavily doped substrate. At 45nm technology node device modeling is performed for PMOS and NMOS with the help of ATLAS to validate the behavior of substrate. Substrate current for heavily and lightly doped substrates is evaluated for PMOS and NMOS devices. Substrate current is more pronounced in the case of heavily doped substrate, making it less suitable at device level. The substrate current in lightly doped substrate device is less than by more than an order when compared to heavily doped device. Therefore the lightly doped substrate devices provides better substrate noise immunity and devices fabricated on lightly doped substrate provides better drain characteristics than heavily doped substrate devices.